In order to cope with an increase in a processing amount, recent memory systems often use memory devices capable of inputting and outputting data in synchronization with clocks, such as a Synchronous Dynamic Random Access Memory (SDRAM). These memory devices input and output data (DQ) in synchronization with rising and falling edges of data strobe signals (DQS).
In particular, data valid periods for the strobe signals tend to be shorter along with increase in the operating frequency of the memory devices. Thus, stable input and output of data is becoming difficult, considering variations in a timing relationship between data and the strobe signals due to the process properties, changes in temperature and voltage, and impedance matching when memory devices are mounted. Under these circumstances, the recent memory systems generally include a function called the ZQ calibration for adjusting the drive capabilities of memory devices.
On the other hand, the memory system in PTL 1 includes a variable delay unit that adjusts a delay amount for a data signal or a strobe signal, using a variable delay element. Accordingly, the memory system in PTL 1 can stably input and output data by adjusting the timing relationship between data and the strobe signals to an appropriate access timing.
In addition, by adjusting the drive capabilities of memory devices, the variable delay element can cover a larger range of the delay amount in which the data can be stably input and output. For example, using the ZQ calibration function for adjusting the drive capability, the drive capability can be adjusted for each chip in consideration of the variations in the impedance matching when the memory devices are mounted. Accordingly, the memory system can more stably input and output data.
With the accelerated increase in the operating frequency of the memory devices in recent years, a period for defining data is becoming shorter. The need for adjusting the access timing with higher precision is growing.
Citation List
Patent Literature
    [PTL 1] Japanese Unexamined Patent Application Publication No. 2004-074623